In dynamic random access memories (DRAMs), typically a single data bit is accessed by a multiplexed row and column address. A row address is received, then a column address is received, both received on the same address pins. This minimizes the number of required pins and the package size. The multiplexing, however, does require more time than for receiving both the row and the column address at the same time. A page mode was introduced whereby a row address would be received then a plurality of consecutive column addresses was received so that a data bit for each column address was provided. This saved time in that a new row address did not have to be received for each new data bit.
A further improvement in speed has been introduced called the nibble mode. For a single row and column address, four consecutive data bits are provided serially. This is a further saving in time not only because only one row address and column address are required but also because all four bits are sensed at the same time and held in respective data latches until serially clocked out in a predetermined sequence. In the page mode, for each new column address, the data bit had to first be transmitted from a latched sense amplifier before it was clocked to the output. A nibble mode circuit is shown in an article entitled "A 100ns 64K Dynamic RAM Using Redundancy Techniques," ISSCC 81, WPM 8.3, pp. 84-85 and U.S. Pat. No. 4,344,156, Eaton, Jr. et al. The circuit described therein uses standard dynamic techniques to achieve the nibble mode.
A complementary row address signal (RAS) goes to a logic low and a row address is received. A complementary column address s1gna1 (CAS) goes to a logic low and a column address is received. This causes a data bit to be provided. This is the conventional method for obtaining a single bit. CAS is then brought to a logic high while keeping RAS at a logic low. This is the method used to establish the nibble mode. In normal operation both RAS and CAS are brought to a logic high to prepare for the next row and column address. In the nibble mode, when CAS is brought to a logic low for the second time, the second data bit in the predetermined sequence is provided. CAS is then brought to a logic high and back to a logic low for the third time to cause the third data bit in the predetermined sequence to be provided. CAS is again brought to a logic high and back to a logic low to cause the fourth data bit in the predetermined sequence to be provided. The nibble mode can be terminated at any time by bringing RAS to a logic high. Each of the four data bits are accessed in response to receiving the row and column address signal and stored in a respective data latch. Upon a falling edge of CAS, the selected data bit is clocked out of the latch, clocked through a data buffer, then out a tri-state driver. Because an output is only valid after CAS is at a logic low, the conventional technique is to begin clocking data out of the data latch and through the data buffer upon the falling edge of CAS. Additionally in DRAMs, a dynamic data buffer is typically used. Such a buffer provides an output in response to a signal generated from CAS. This signal clocks the output through the buffer to a tri-state driver subsequent to the falling edge of CAS. Using these conventional dynamic techniques, however, does require taking time for the data bit to propagate from the data latch to the input of the tri-state driver after the falling edge of CAS. Accordingly, there is a delay in the access time from when CAS goes to a logic low and when the output is valid.